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What is a JTAG port on a processor?
We have seen many chips, each with a JTAG port, what is it for?
JTAG (Joint Test Action Group) Joint Test Action Group. This is a standard test protocol that is mainly used for in-circuit testing and is compatible with IEEE 1149.1 protocol. Many modern chips have this protocol, like FPGA, DSP, etc.
At first, JTAG port was only used to test inside of chip. Its principle is to define a test access port named TAP (Test Access Port) inside device, and then use a special tool to test inside. . Now all parts inside chip can be programmed and controlled via JTAG.
Let's imagine JTAG port interface definition! There are many packages for JTAG port such as 10-pin, 14-pin and 20-pin. Although number and order of contacts vary, they are all same. similar!
IEEE1149.1 is mandatory in following cases:
1. TCK (Test Clock Input) - clock output of JTAG port
The test clock input pin provides an independent and master clock for TAP operation, and all TAP operations are driven by this clock.
2. TMS (Test Mode Selection Input) -----Test Mode Selection Input
The TMS signal can control TAP to switch between different states, and this signal is valid on rising edge of TCK.
3. TDI (test data input) ----- test data input contact
TDI is a serial input interface for entering all data into specific registers.
4. TDO (Test Data Output) -----Test Data Output Contact
TDO is an interface for serial output of all data that should be output from certain registers.
5. (VTREF) ----- Interface Signal Level
The interface signal level can be used to determine logic level used by ARM JTAG interface.
Additional IEEE1149.1 requirements:
1. TRST (Reset test input) ---- Reset test input pin
The TRST signal can perform same function as TMS, which is used to reset (initialize) TAPController.
2. RTCK (Return Test Clock) - feedback test clock
This pin is used to clock TCK signal. The clock signal returned by target end back to emulator is directly grounded when not in use.
3. nSRST (system reset) --- clock reset signal feedback pin
This pin can detect reset situation of target system, and can also be connected to system reset signal on target board to reset target system directly. It is recommended to add an appropriate pull-up resistor to target to prevent false triggering.
4. USER IN
This pin can be connected to IO of target computer totake control from host computer.
5. USER OUT - user-defined output
This pin can be connected to IO of target computer to send status information to host computer.
In fact, these additional pins are not normally used. The 20-wire ports that appear in practical applications are mainly designed to increase ground wires and reduce JTAG interference.